module insDecoder (
    input   logic   [31:0]          inst,
    output  logic   [5:0]           op,
    output  logic   [4:0]           rs,
    output  logic   [4:0]           rt,
    output  logic   [4:0]           rd,
    output  logic   [5:0]           func,
    output  logic   [15:0]          imm,
    output  logic   [25:0]          addr
);


always_comb begin
    op = inst[31:26];
end

always_comb begin
    case (op)
        6'b000000: begin : R_Type
            rs      = inst[25:21];
            rt      = inst[20:16];
            rd      = inst[15:11];
            func    = inst[5:0];
            imm     = 16'd0;
            addr    = 26'd0;
        end
        6'b001000,  // addi
        6'b001100,  // andi
        6'b001110,  // xori
        6'b001011,  // sltiu
        6'b100011,  // lw
        6'b101011,  // sw
        6'b000100,  // beq
        6'b000101:  // bne
        begin : I_Type
            rs      = inst[25:21];
            rt      = inst[20:16];
            rd      = 5'd0;
            func    = 6'd0;
            imm     = inst[15:0];
            addr    = 26'd0;
        end
        6'b000010,  // j
        6'b000011:  // jal
        begin : J_Type
            rs      = 5'd0;
            rt      = 5'd0;
            rd      = 5'd0;
            func    = 6'd0;
            imm     = 16'd0;
            addr    = inst[25:0];
        end
        default: begin
            rs      = 5'd0;
            rt      = 5'd0;
            rd      = 5'd0;
            func    = 6'd0;
            imm     = 16'd0;
            addr    = 26'd0;
        end
    endcase
end
endmodule
